The present invention relates to a liquid crystal display device; and, more particularly, the invention relates to a liquid crystal display device in which gate signal lines, drain signal lines and counter voltage signal lines are formed on a liquid-crystal-side surface of one of a pair of substrates which are arranged to face each other with liquid crystal material disposed therebetween.
For example, in a so-called lateral-electric field type (IPS type) liquid crystal display device, pixels are formed on a liquid crystal side of one substrate, and each pixel includes a pixel electrode and a counter electrode, whereby an electric field is generated between the counter electrode and the pixel electrode.
Further, video signals are supplied to the pixel electrode from a drain signal line by way of a switching element which is driven in response to a scanning signal received from a gate signal line, while a reference signal, which becomes the reference with respect to the above-mentioned video signals, is supplied to the counter electrodes through counter voltage signal lines.
Here, as shown in FIG. 53, on a liquid-crystal-side of one substrate, for example, the above-mentioned gate signal lines GL1, GL2, . . . , GLn are usually configured such that they extend in the x direction and are arranged in parallel in the y direction, while the above-mentioned drain signal lines DL1, DL2, . . . , DLn are usually configured such that they extend in the y direction and are arranged in parallel in the x direction. Further, counter voltage signal lines CL1, CL2, . . . , CLn are usually arranged between respective gate signal lines GL1, GL2, . . . , GLn such that the counter voltage signal lines CL1, CL2, . . . , CLn are arranged substantially parallel to the gate signal lines GL1, GL2, . . . , GLn.
Here, the respective gate signal lines GL1, GL2, . . . , GLn are, for example, sequentially selected in response to scanning signals supplied from a scanning signal driver circuit V which is connected with one end of each of the respective gate signal lines GL1, GL2, . . . , GLn. In conformity with this selection timing, to the respective drain signal lines DL1, DL2, . . . , DLn, for example, the video signals are supplied from a video signal driver circuit He which is connected with one end of each of the drain signal lines DL1, DL2, . . . , DLn. The respective counter voltage signal lines CL1, CL2, . . . , CLn have, for example, one end thereof connected in common, and, hence, a reference signal is supplied to the respective counter voltage signal lines CL1, CL2, . . . , CLn. Such a technique is disclosed in Japanese Unexamined Patent Publication Hei11(1999)-271788.